01
Hardware security
What accelerators leak through power, and how far an attacker can get with it. Side-channel analysis of ADCs in analog in-memory computing, weight extraction, and model-protection trade-offs.
0x0000 PhD candidate · Leiden University
Roozbeh Siyadatzadeh
Hardware security, embedded AI, FPGA design
I study what edge-AI hardware leaks through its power consumption, and how to design in-memory computing chips that do not.
Where does hardware meet trustworthy AI?
Four threads run through the work: what physical systems leak, how to run machine learning inside tight budgets, how to build the hardware, and how to keep systems reliable while doing it.
02
Efficient embedded AI
Machine learning under tight compute, memory, and energy budgets: transfer learning for data-poor embedded deployments, distributed CNN inference at the edge, and RISC-V implementation.
03
FPGA and hardware design
From RTL to a working accelerator: Verilog and VHDL designs, verification, and neural-network inference pipelines mapped onto FPGAs.
04
Dependable systems
Scheduling and learning techniques for systems that must stay reliable, on time, and within a power budget: fault-tolerant fog computing, aging-aware multicore replication, and heterogeneous real-time scheduling.
My PhD project
Security assessment of an in-memory computing chip: what it leaks, and how much of a model that gives away.
NeuroSoC, a Horizon Europe project (grant 101070634), built a system-on-chip that pairs a phase-change-memory analog in-memory computing unit with RISC-V cores in 28 nm FD-SOI.
Leiden University owned the security assessment, in a work package shared with IBM and STMicroelectronics France and Italy; the closest collaboration on the security task was with ST France. My part: what the analog tiles and their ADCs leak through power, how much of a model can be recovered from it, and what that means for protecting models on the chip.
Partners IBM · STMicroelectronics · Bosch · Thales · Ubotica · Benkei · Software Competence Center Hagenberg (SCCH) · ETH Zurich · Leiden University · University of Bologna · University of Patras · University of Pavia · King's College London · Northeastern University London
- 0x0104TraceFormerEuromicro DSD 2025
- 0x0106P2WACM SAC 2026
- 0x0105CNN partitioning securitySPACE 2025 (LNCS)
Peer-reviewed papers
P2W: From Power Traces to Weights Matrix - An Unconventional Transfer Learning Approach
Turns power traces captured from an embedded SoC into an approximate weight matrix that initialises a new model when the original model and its training data are out of reach.
A Security Analysis of CNN Partitioning Strategies for Distributed Inference at the Edge
Compares vertical, horizontal, and data partitioning of CNNs across edge devices against an eavesdropper who reconstructs the input image from intercepted intermediate data.
TraceFormer: A Transformer-Based Method for Weight Extraction from AIMC Tiles
Shows that the weights stored in an analog in-memory computing tile can be recovered from the power consumption of its ADCs, using a Transformer and an input-controlled weight-isolation technique.
ReLIEF: A Reinforcement-Learning-Based Real-Time Task Assignment Strategy in Emerging Fault-Tolerant Fog Computing
Reinforcement learning assigns primary and backup copies of real-time tasks to fog nodes, balancing communication delay against the workload on each device.
ATLAS: Aging-Aware Task Replication for Multicore Safety-Critical Systems
Aging-aware task replication that keeps periodic hard real-time tasks at their reliability target over a multicore system’s lifetime while limiting the temperature that accelerates aging.
Passive Primary/Backup-Based Scheduling for Simultaneous Power and Reliability Management on Heterogeneous Embedded Systems
Passive primary/backup scheduling on heterogeneous multicores that mixes task mapping across core types and runs backups after primaries to remove execution overlap.
Research and engineering
NeuroSoC: security assessment of an in-memory computing SoC
Side-channel security assessment of a PCM-based analog in-memory computing system-on-chip developed by a Horizon Europe consortium of industry and academic partners.
Thermal management and task scheduling for multicore systems
How task placement and scheduling shape the thermal behaviour of a multicore system, evaluated with a gem5, McPAT, and HotSpot workflow.
Reinforcement-learning DVFS manager for multicore platforms
A reinforcement-learning controller for dynamic voltage and frequency scaling, evaluated on a simulated multicore with Sniper, McPAT, and HotSpot.
Distributed Keras inference over gRPC
A prototype prediction service that coordinates Keras model inference across networked Python processes with gRPC.
Education, teaching, skills
Education
PhD Computer Science
Leiden University · Nov 2022 – present
MSc Computer Architecture
Sharif University of Technology · Sept 2020 – Aug 2022
BSc Computer Engineering
Persian Gulf University · Sept 2016 – Aug 2020
Teaching
Embedded Systems and Software
Lab instructor · Leiden University
Fundamentals of Digital Systems Design
Teaching assistant · Leiden University
Digital System Design
Teaching assistant · Sharif University of Technology
Digital System Design Laboratory
Lab instructor · Sharif University of Technology
Skills
Hardware and architecture
Side-channel analysis, Analog in-memory computing, FPGA (Verilog, VHDL, Vivado), RISC-V SoCs, Real-time scheduling, gem5, Sniper, McPAT, HotSpot
Machine learning
PyTorch, TensorFlow, Transformers, Reinforcement learning, OpenCV
Programming
Python, Rust, C, C++, Java, Julia, Clojure, Assembly
Tools and infrastructure
Linux, Git, gRPC, MATLAB, SQL and MongoDB, Lex, Yacc, Bison
Awards
Ranked 2nd of 25 MSc Computer Architecture students
Sharif University of Technology · 2022
Direct admission to graduate school
Sharif University of Technology · 2020
Exceptionally talented student
Ministry of Science · 2020
Outstanding student award
Persian Gulf University · 2019
2nd place, national robotics competition (firefighter robot)
Shiraz · 2014
3rd place, national robotics competition (fighter robot)
Shiraz · 2013
My notes
Security Challenges in Analog In-Memory Computing
How ADC power leakage can expose weights stored in analog in-memory-computing accelerators, and what that means for secure edge AI.
From Power Traces to Model Weights: P2W and TraceFormer
Two research methods for learning about embedded neural-network weights through physical power side channels.
Reinforcement Learning for Reliable Real-Time Fog Systems
How ReLIEF assigns primary and backup tasks while balancing deadlines, failures, communication delay, and fog-node workload.