# Roozbeh Siyadatzadeh: full site content > Roozbeh Siyadatzadeh is a PhD candidate at Leiden University working on hardware security for embedded AI: power side-channel analysis of analog in-memory computing, model extraction, FPGA and RISC-V systems, and dependable real-time computing. This document concatenates every record of https://roozbeh.nl (content updated 2026-09-06). Each section is a Markdown document with YAML frontmatter from the Open Knowledge Format bundle at https://roozbeh.nl/okf/. A short index is at https://roozbeh.nl/llms.txt. --- type: Person title: Roozbeh Siyadatzadeh description: PhD candidate at Leiden University; hardware security, embedded ai, fpga design. resource: https://orcid.org/0000-0002-2258-4110 tags: - person - researcher - hardware-security - embedded-ai - computer-architecture generated: by: process:roozbeh.nl/astro-build at: 2026-09-06T00:00:00Z status: stable stale_after: 2027-03-01T00:00:00Z sources: - id: cv resource: https://roozbeh.nl/cv.pdf title: Curriculum vitae (PDF) author: human:roozbeh - id: orcid resource: https://orcid.org/0000-0002-2258-4110 title: ORCID record - id: leiden resource: https://www.universiteitleiden.nl/en/staffmembers/roozbeh-siyadatzadeh title: Leiden University staff profile name: Roozbeh Siyadatzadeh given_name: Roozbeh family_name: Siyadatzadeh orcid: 0000-0002-2258-4110 email: s.r.siyadatzadeh@liacs.leidenuniv.nl location: The Netherlands affiliation: Leiden Institute of Advanced Computer Science (LIACS), Leiden University homepage: https://roozbeh.nl profiles: LinkedIn: https://www.linkedin.com/in/roozbeh24/ GitHub: https://github.com/Roozbeh-Sdtz Google Scholar: https://scholar.google.com/citations?user=4mz_3_YAAAAJ&hl=en ORCID: https://orcid.org/0000-0002-2258-4110 ResearchGate: https://www.researchgate.net/profile/Roozbeh-Siyadatzadeh-2 Leiden University: https://www.universiteitleiden.nl/en/staffmembers/roozbeh-siyadatzadeh --- # Roozbeh Siyadatzadeh Roozbeh Siyadatzadeh is a PhD candidate at Leiden University working on hardware security for embedded AI: power side-channel analysis of analog in-memory computing, model extraction, FPGA and RISC-V systems, and dependable real-time computing. # Positions * **PhD candidate**, Leiden University, LIACS (Nov 2022 – present). Security assessment of an analog in-memory computing SoC within the Horizon Europe NeuroSoC project: ADC power side-channel analysis, weight extraction, and power-trace-based transfer learning. * **Graduate researcher**, Embedded Systems Research Laboratory, Sharif University of Technology (Sept 2020 – Aug 2022). Reinforcement-learning task assignment for fault-tolerant fog computing, aging-aware replication for safety-critical multicores, and power-aware primary/backup scheduling. # Education * **PhD Computer Science**, Leiden University, The Netherlands (Nov 2022 – present). Hardware security of analog in-memory computing, within the NeuroSoC project. Advisors: Prof. Nele Mentens, Dr. Todor Stefanov. * **MSc Computer Architecture**, Sharif University of Technology, Tehran (Sept 2020 – Aug 2022). Embedded Systems Research Laboratory (ESRLab). Thesis: Reinforcement learning-based task assignment in fog computing. Advisors: Prof. Alireza Ejlali. * **BSc Computer Engineering**, Persian Gulf University, Bushehr (Sept 2016 – Aug 2020). Computer systems and neural networks. # Publications * [P2W: From Power Traces to Weights Matrix - An Unconventional Transfer Learning Approach](../publications/p2w-power-traces-to-weights.md) (ACM SAC 2026, 2026). Turns power traces captured from an embedded SoC into an approximate weight matrix that initialises a new model when the original model and its training data are out of reach. * [A Security Analysis of CNN Partitioning Strategies for Distributed Inference at the Edge](../publications/security-analysis-cnn-partitioning-edge.md) (SPACE 2025 (LNCS), 2026). Compares vertical, horizontal, and data partitioning of CNNs across edge devices against an eavesdropper who reconstructs the input image from intercepted intermediate data. * [TraceFormer: A Transformer-Based Method for Weight Extraction from AIMC Tiles](../publications/traceformer-weight-extraction-aimc.md) (Euromicro DSD 2025, 2025). Shows that the weights stored in an analog in-memory computing tile can be recovered from the power consumption of its ADCs, using a Transformer and an input-controlled weight-isolation technique. * [ReLIEF: A Reinforcement-Learning-Based Real-Time Task Assignment Strategy in Emerging Fault-Tolerant Fog Computing](../publications/relief-rl-task-assignment-fog.md) (IEEE IoT Journal, 2023). Reinforcement learning assigns primary and backup copies of real-time tasks to fog nodes, balancing communication delay against the workload on each device. * [ATLAS: Aging-Aware Task Replication for Multicore Safety-Critical Systems](../publications/atlas-aging-aware-task-replication.md) (IEEE RTAS 2023, 2023). Aging-aware task replication that keeps periodic hard real-time tasks at their reliability target over a multicore system’s lifetime while limiting the temperature that accelerates aging. * [Passive Primary/Backup-Based Scheduling for Simultaneous Power and Reliability Management on Heterogeneous Embedded Systems](../publications/passive-primary-backup-scheduling-heterogeneous.md) (IEEE T-SUSC, 2023). Passive primary/backup scheduling on heterogeneous multicores that mixes task mapping across core types and runs backups after primaries to remove execution overlap. # Projects * [NeuroSoC: security assessment of an in-memory computing SoC](../projects/neurosoc.md) (Nov 2022 – Feb 2026). Side-channel security assessment of a PCM-based analog in-memory computing system-on-chip developed by a Horizon Europe consortium of industry and academic partners. * [Thermal management and task scheduling for multicore systems](../projects/thermal-aware-task-scheduling.md) (Jun 2021 – Jun 2021). How task placement and scheduling shape the thermal behaviour of a multicore system, evaluated with a gem5, McPAT, and HotSpot workflow. * [Complex-number ALU on FPGA](../projects/complex-alu-fpga.md) (May 2021 – May 2021). A VHDL arithmetic logic unit for complex-number operations, synthesised and verified with Xilinx ISE. * [Neural-network inference on FPGA](../projects/deep-learning-on-fpga.md) (Jan 2021 – Jan 2021). An RTL implementation of neural-network inference for resource-constrained edge hardware. * [Reinforcement-learning DVFS manager for multicore platforms](../projects/rl-dvfs-manager.md) (Dec 2020 – Dec 2020). A reinforcement-learning controller for dynamic voltage and frequency scaling, evaluated on a simulated multicore with Sniper, McPAT, and HotSpot. * [Distributed VSOP87 planetary positions with MPI](../projects/distributed-vsop87.md) (Nov 2020 – Nov 2020). The VSOP87 planetary-position calculation parallelised across MPI workers in C. * [FPGA CNN for ECG classification](../projects/fpga-cnn-ecg-classification.md) (Apr 2020 – Apr 2020). A convolutional-neural-network pipeline for ECG classification, from a TensorFlow model to an RTL implementation. * [Distributed Keras inference over gRPC](../projects/distributed-keras-inference.md) (Feb 2020 – Feb 2020). A prototype prediction service that coordinates Keras model inference across networked Python processes with gRPC. * [Facial attribute editing with a GAN](../projects/facial-attribute-editing-gan.md) (Oct 2019 – Oct 2019). Controlled facial-attribute editing with a generative adversarial network in TensorFlow. * [Sentiment analysis of social-media comments](../projects/social-media-sentiment-analysis.md) (Aug 2019 – Aug 2019). Machine-learning sentiment classification of social-media comments in TensorFlow. # Teaching * Lab instructor, Embedded Systems and Software, Leiden University (Spring 2024, Spring 2025). * Teaching assistant, Fundamentals of Digital Systems Design, Leiden University (Fall 2023, Fall 2024). * Teaching assistant, Digital System Design, Sharif University of Technology (Spring 2022). * Lab instructor, Digital System Design Laboratory, Sharif University of Technology (Summer 2021). # Skills * **Hardware and architecture:** Side-channel analysis, Analog in-memory computing, FPGA (Verilog, VHDL, Vivado), RISC-V SoCs, Real-time scheduling, gem5, Sniper, McPAT, HotSpot. * **Machine learning:** PyTorch, TensorFlow, Transformers, Reinforcement learning, OpenCV. * **Programming:** Python, Rust, C, C++, Java, Julia, Clojure, Assembly. * **Tools and infrastructure:** Linux, Git, gRPC, MATLAB, SQL and MongoDB, Lex, Yacc, Bison. # Awards * Ranked 2nd of 25 MSc Computer Architecture students, Sharif University of Technology, 2022. * Direct admission to graduate school, Sharif University of Technology, 2020. * Exceptionally talented student, Ministry of Science, 2020. * Outstanding student award, Persian Gulf University, 2019. * 1st place, tourism startup weekend, Jam, 2018. * 2nd place, healthcare startup weekend, Bushehr, 2017. * 1st place, provincial robotics competition (firefighter robot), Fasa, 2015. * 2nd place, national robotics competition (firefighter robot), Shiraz, 2014. * 3rd place, national robotics competition (fighter robot), Shiraz, 2013. # Languages * English: Professional working proficiency. * Dutch: A2 elementary proficiency. * Persian: Native. # Notes * [Security Challenges in Analog In-Memory Computing](../notes/imc-security.md) (2024-12-15). How ADC power leakage can expose weights stored in analog in-memory-computing accelerators, and what that means for secure edge AI. * [From Power Traces to Model Weights: P2W and TraceFormer](../notes/weight-extraction.md) (2024-11-28). Two research methods for learning about embedded neural-network weights through physical power side channels. * [Reinforcement Learning for Reliable Real-Time Fog Systems](../notes/rl-realtime.md) (2024-10-12). How ReLIEF assigns primary and backup tasks while balancing deadlines, failures, communication delay, and fog-node workload. * [Phase-Change Memory for Analog In-Memory Computing](../notes/pcm-future.md) (2024-09-05). A practical introduction to PCM conductance, neural-network acceleration, engineering trade-offs, and physical security. * [My Journey from Bushehr to Leiden](../notes/academic-journey.md) (2024-07-18). Reflections on my academic path from Bushehr to the Netherlands. --- --- type: Scholarly Article title: "P2W: From Power Traces to Weights Matrix - An Unconventional Transfer Learning Approach" description: Turns power traces captured from an embedded SoC into an approximate weight matrix that initialises a new model when the original model and its training data are out of reach. resource: https://doi.org/10.1145/3748522.3779939 tags: - embedded machine learning - power side channels - transfer learning - model extraction - system-on-chip - power side-channel analysis generated: by: process:roozbeh.nl/astro-build at: 2026-09-06T00:00:00Z status: stable sources: - id: crossref resource: https://api.crossref.org/works/10.1145/3748522.3779939 title: Crossref metadata record - id: publisher resource: https://doi.org/10.1145/3748522.3779939 title: Publisher record (ACM) - id: pdf resource: https://roozbeh.nl/papers/P2W.pdf title: arXiv preprint, Feb 2025 (PDF) - id: preprint resource: https://arxiv.org/abs/2502.14968 title: arXiv:2502.14968 doi: 10.1145/3748522.3779939 authors: - name: Roozbeh Siyadatzadeh orcid: 0000-0002-2258-4110 - name: Fatemeh Mehrafrooz orcid: 0000-0001-5844-3793 - name: Nele Mentens orcid: 0000-0001-8753-7895 - name: Todor Stefanov orcid: 0000-0001-6006-9366 year: 2026 published: 2026-03-23 venue: Proceedings of the 41st ACM/SIGAPP Symposium on Applied Computing (SAC 2026) venue_type: conference publisher: ACM pages: 653-661 web_page: https://roozbeh.nl/publications/p2w-power-traces-to-weights/ pdf: https://roozbeh.nl/papers/P2W.pdf pdf_version: preprint bibtex: https://roozbeh.nl/publications/p2w-power-traces-to-weights.bib license: https://creativecommons.org/licenses/by/4.0/ funding: - Horizon Europe project NeuroSoC (European Union, grant 101070634) citation_count: 0 citation_count_source: Semantic Scholar Graph API, 2026-09-02 --- # P2W: From Power Traces to Weights Matrix - An Unconventional Transfer Learning Approach Roozbeh Siyadatzadeh, Fatemeh Mehrafrooz, Nele Mentens, Todor Stefanov. Proceedings of the 41st ACM/SIGAPP Symposium on Applied Computing (SAC 2026), 2026, pp. 653-661. DOI: [10.1145/3748522.3779939](https://doi.org/10.1145/3748522.3779939). # Abstract The rapid growth of deploying machine learning (ML) models within embedded systems on a chip (SoCs) has led to transformative shifts in fields like healthcare and autonomous vehicles. One of the primary challenges for training such embedded ML models is the lack of publicly available high-quality training data. Transfer learning approaches address this challenge by utilizing the knowledge encapsulated in an existing ML model as a starting point for training a new ML model. However, existing transfer learning approaches require direct access to the existing model which is not always feasible, especially for ML models deployed on embedded SoCs. Therefore, in this paper, we introduce a novel unconventional transfer learning approach to train a new ML model by extracting and using weights from an existing ML model running on an embedded SoC without having access to the model within the SoC. Our approach captures power consumption measurements from the SoC while it is executing the ML model and translates them to an approximated weights matrix used to initialize the new ML model. This improves the learning efficiency and predictive performance of the new model, especially in scenarios with limited data available to train the model. Our novel approach can effectively increase the accuracy of the new ML model up to 3 times compared to classical training methods using the same amount of limited training data. # Key result Up to 3 times higher accuracy than classical training on the same limited dataset, without any access to the model inside the SoC. # Cite R. Siyadatzadeh, F. Mehrafrooz, N. Mentens and T. Stefanov, "P2W: From Power Traces to Weights Matrix - An Unconventional Transfer Learning Approach," in Proceedings of the 41st ACM/SIGAPP Symposium on Applied Computing (SAC 2026), Thessaloniki, Greece, 2026, pp. 653-661, doi: 10.1145/3748522.3779939. ```bibtex @inproceedings{siyadatzadeh2026p2w, author = {Siyadatzadeh, Roozbeh and Mehrafrooz, Fatemeh and Mentens, Nele and Stefanov, Todor}, title = {{P2W}: From Power Traces to Weights Matrix - An Unconventional Transfer Learning Approach}, booktitle = {Proceedings of the 41st ACM/SIGAPP Symposium on Applied Computing (SAC 2026)}, year = {2026}, pages = {653--661}, publisher = {ACM}, address = {Thessaloniki, Greece}, doi = {10.1145/3748522.3779939}, url = {https://doi.org/10.1145/3748522.3779939}, } ``` # Files * [Web page](https://roozbeh.nl/publications/p2w-power-traces-to-weights/) * [arXiv preprint, Feb 2025 (PDF)](https://roozbeh.nl/papers/P2W.pdf) * [arXiv:2502.14968](https://arxiv.org/abs/2502.14968) * [AI-generated audio overview (NotebookLM), 5 min](https://roozbeh.nl/audio/P2W.m4a) * [AI-generated video overview (NotebookLM), 7 min](https://roozbeh.nl/videos/P2W.mp4) # Related * [NeuroSoC: security assessment of an in-memory computing SoC](../projects/neurosoc.md) * [Security Challenges in Analog In-Memory Computing](../notes/imc-security.md) * [From Power Traces to Model Weights: P2W and TraceFormer](../notes/weight-extraction.md) Author record: [Roozbeh Siyadatzadeh](../person/roozbeh-siyadatzadeh.md). --- --- type: Scholarly Article title: A Security Analysis of CNN Partitioning Strategies for Distributed Inference at the Edge description: Compares vertical, horizontal, and data partitioning of CNNs across edge devices against an eavesdropper who reconstructs the input image from intercepted intermediate data. resource: https://doi.org/10.1007/978-3-032-16342-4_15 tags: - distributed edge ai - cnn security - model partitioning - input reconstruction - privacy - distributed edge computing - neural networks - security generated: by: process:roozbeh.nl/astro-build at: 2026-09-06T00:00:00Z status: stable sources: - id: crossref resource: https://api.crossref.org/works/10.1007/978-3-032-16342-4_15 title: Crossref metadata record - id: publisher resource: https://doi.org/10.1007/978-3-032-16342-4_15 title: Publisher record (Springer Nature Switzerland) - id: pdf resource: https://roozbeh.nl/papers/SPACE_25.pdf title: Author manuscript (PDF) doi: 10.1007/978-3-032-16342-4_15 authors: - name: Fatemeh Mehrafrooz orcid: 0000-0001-5844-3793 - name: Roozbeh Siyadatzadeh orcid: 0000-0002-2258-4110 - name: Nele Mentens orcid: 0000-0001-8753-7895 - name: Todor Stefanov orcid: 0000-0001-6006-9366 year: 2026 published: 2026-02-12 venue: Security, Privacy, and Applied Cryptography Engineering (SPACE 2025) venue_type: book-chapter publisher: Springer Nature Switzerland volume: "16406" pages: 262-281 web_page: https://roozbeh.nl/publications/security-analysis-cnn-partitioning-edge/ pdf: https://roozbeh.nl/papers/SPACE_25.pdf pdf_version: author bibtex: https://roozbeh.nl/publications/security-analysis-cnn-partitioning-edge.bib citation_count: 0 citation_count_source: Semantic Scholar Graph API, 2026-09-02 --- # A Security Analysis of CNN Partitioning Strategies for Distributed Inference at the Edge Fatemeh Mehrafrooz, Roozbeh Siyadatzadeh, Nele Mentens, Todor Stefanov. Security, Privacy, and Applied Cryptography Engineering (SPACE 2025), 2026, pp. 262-281. DOI: [10.1007/978-3-032-16342-4_15](https://doi.org/10.1007/978-3-032-16342-4_15). # Abstract The inference of Convolutional Neural Networks (CNNs) at the Edge poses significant challenges due to resource limitations of edge devices. One approach to addressing these challenges is to distribute a CNN model across multiple edge devices. While much attention has been paid to improving the performance, memory utilization, energy efficiency, and robustness of distributed CNN inference at the Edge, security implications of such inference remain largely unexplored. Therefore, in this paper, we investigate the security vulnerabilities of the three main partitioning strategies for distributing CNN models across multiple edge devices, namely vertical partitioning, horizontal partitioning, and data partitioning. More specifically, we assess how accurately an attacker can reconstruct the input image given to a CNN model and predict the image class by eavesdropping on the communication link between two edge devices. We devise a simple, yet realistic attack scenario in which the attacker attempts to reconstruct the input image from intermediate data obtained from the communication link. In order to evaluate the vulnerability of the system, the reconstructed image is fed back into the model to see if its class can be determined. We conduct extensive experiments using different CNN models and datasets. Our results show that data partitioning is less vulnerable to this attack scenario compared to the other partitioning strategies, while vertical partitioning is the most vulnerable. # Key result Data partitioning leaked the least reconstructable input information, while vertical partitioning was the most vulnerable across the evaluated models and datasets. # Cite F. Mehrafrooz, R. Siyadatzadeh, N. Mentens and T. Stefanov, "A Security Analysis of CNN Partitioning Strategies for Distributed Inference at the Edge," in Security, Privacy, and Applied Cryptography Engineering (SPACE 2025) (Lecture Notes in Computer Science, vol. 16406), Guwahati, India, 2026, pp. 262-281, doi: 10.1007/978-3-032-16342-4_15. ```bibtex @inproceedings{mehrafrooz2025partitioning, author = {Mehrafrooz, Fatemeh and Siyadatzadeh, Roozbeh and Mentens, Nele and Stefanov, Todor}, title = {A Security Analysis of {CNN} Partitioning Strategies for Distributed Inference at the Edge}, booktitle = {Security, Privacy, and Applied Cryptography Engineering (SPACE 2025)}, series = {Lecture Notes in Computer Science}, volume = {16406}, year = {2026}, pages = {262--281}, publisher = {Springer Nature Switzerland}, address = {Guwahati, India}, doi = {10.1007/978-3-032-16342-4_15}, url = {https://doi.org/10.1007/978-3-032-16342-4_15}, } ``` # Files * [Web page](https://roozbeh.nl/publications/security-analysis-cnn-partitioning-edge/) * [Author manuscript (PDF)](https://roozbeh.nl/papers/SPACE_25.pdf) * [AI-generated audio overview (NotebookLM), 5 min](https://roozbeh.nl/audio/SPACE_25.m4a) * [AI-generated video overview (NotebookLM), 8 min](https://roozbeh.nl/videos/SPACE_25.mp4) Author record: [Roozbeh Siyadatzadeh](../person/roozbeh-siyadatzadeh.md). --- --- type: Scholarly Article title: "TraceFormer: A Transformer-Based Method for Weight Extraction from AIMC Tiles" description: Shows that the weights stored in an analog in-memory computing tile can be recovered from the power consumption of its ADCs, using a Transformer and an input-controlled weight-isolation technique. resource: https://doi.org/10.1109/DSD67783.2025.00092 tags: - analog in-memory computing - hardware security - power side channels - transformers - weight extraction - vulnerabilities - power side-channel analysis - adc power analysis generated: by: process:roozbeh.nl/astro-build at: 2026-09-06T00:00:00Z status: stable sources: - id: crossref resource: https://api.crossref.org/works/10.1109/DSD67783.2025.00092 title: Crossref metadata record - id: publisher resource: https://doi.org/10.1109/DSD67783.2025.00092 title: Publisher record (IEEE) - id: pdf resource: https://roozbeh.nl/papers/TraceFormer.pdf title: Author manuscript (PDF) doi: 10.1109/DSD67783.2025.00092 authors: - name: Roozbeh Siyadatzadeh orcid: 0000-0002-2258-4110 - name: Fatemeh Mehrafrooz orcid: 0000-0001-5844-3793 - name: Nele Mentens orcid: 0000-0001-8753-7895 - name: Todor Stefanov orcid: 0000-0001-6006-9366 year: 2025 published: 2025-09-10 venue: 2025 28th Euromicro Conference on Digital System Design (DSD) venue_type: conference publisher: IEEE pages: 635-642 web_page: https://roozbeh.nl/publications/traceformer-weight-extraction-aimc/ pdf: https://roozbeh.nl/papers/TraceFormer.pdf pdf_version: author bibtex: https://roozbeh.nl/publications/traceformer-weight-extraction-aimc.bib funding: - Horizon Europe project NeuroSoC (European Union, grant 101070634) citation_count: 0 citation_count_source: Semantic Scholar Graph API, 2026-09-02 --- # TraceFormer: A Transformer-Based Method for Weight Extraction from AIMC Tiles Roozbeh Siyadatzadeh, Fatemeh Mehrafrooz, Nele Mentens, Todor Stefanov. 2025 28th Euromicro Conference on Digital System Design (DSD), 2025, pp. 635-642. DOI: [10.1109/DSD67783.2025.00092](https://doi.org/10.1109/DSD67783.2025.00092). # Abstract Analog In-Memory Computing (AIMC) has emerged as a promising solution to address the performance and energy efficiency limitations of conventional von Neumann architectures for machine learning (ML) applications. This promising approach relies on analog-to-digital converters (ADCs) to enable the integration of AIMC tiles into larger digital systems. In this paper, we investigate the vulnerability of AIMC tiles to power side-channel attacks targeting these ADCs. Specifically, we demonstrate that the numerical values of weights stored in an AIMC tile, that are often a critical asset of an ML model, can be extracted by analyzing the power consumption of the ADCs. With this objective in mind, we propose TraceFormer, which is a two-phase method: 1) we train a Transformer neural network (NN) model to translate captured ADC power traces into digital output values; 2) we utilize a novel input-controlled weight isolation technique in order to isolate each individual weight within the AIMC tile, and then reveal the isolated weight’s value by ADC power side-channel analysis using the Transformer NN model. We demonstrate the practical applicability and robustness of our proposed method by power side-channel analysis of Oscillator-based ADCs that are typically integrated within AIMC tiles. The experimental results show high accuracy and robustness of our Transformer-based analysis, implying potential vulnerabilities in AIMC tiles. # Key result High extraction accuracy and robustness on oscillator-based ADCs emulated on real hardware, exposing a new attack surface in AIMC tiles. # Cite R. Siyadatzadeh, F. Mehrafrooz, N. Mentens and T. Stefanov, "TraceFormer: A Transformer-Based Method for Weight Extraction from AIMC Tiles," in 2025 28th Euromicro Conference on Digital System Design (DSD), Salerno, Italy, 2025, pp. 635-642, doi: 10.1109/DSD67783.2025.00092. ```bibtex @inproceedings{siyadatzadeh2025traceformer, author = {Siyadatzadeh, Roozbeh and Mehrafrooz, Fatemeh and Mentens, Nele and Stefanov, Todor}, title = {{TraceFormer}: A Transformer-Based Method for Weight Extraction from {AIMC} Tiles}, booktitle = {2025 28th Euromicro Conference on Digital System Design (DSD)}, year = {2025}, pages = {635--642}, publisher = {IEEE}, address = {Salerno, Italy}, doi = {10.1109/DSD67783.2025.00092}, url = {https://doi.org/10.1109/DSD67783.2025.00092}, } ``` # Files * [Web page](https://roozbeh.nl/publications/traceformer-weight-extraction-aimc/) * [Author manuscript (PDF)](https://roozbeh.nl/papers/TraceFormer.pdf) * [AI-generated audio overview (NotebookLM), 4 min](https://roozbeh.nl/audio/TraceFormer.m4a) * [AI-generated video overview (NotebookLM), 8 min](https://roozbeh.nl/videos/TraceFormer.mp4) # Related * [NeuroSoC: security assessment of an in-memory computing SoC](../projects/neurosoc.md) * [Security Challenges in Analog In-Memory Computing](../notes/imc-security.md) * [From Power Traces to Model Weights: P2W and TraceFormer](../notes/weight-extraction.md) * [Phase-Change Memory for Analog In-Memory Computing](../notes/pcm-future.md) Author record: [Roozbeh Siyadatzadeh](../person/roozbeh-siyadatzadeh.md). --- --- type: Scholarly Article title: "ReLIEF: A Reinforcement-Learning-Based Real-Time Task Assignment Strategy in Emerging Fault-Tolerant Fog Computing" description: Reinforcement learning assigns primary and backup copies of real-time tasks to fog nodes, balancing communication delay against the workload on each device. resource: https://doi.org/10.1109/JIOT.2023.3240007 tags: - reinforcement learning - fog computing - real-time systems - fault tolerance - resource allocation - internet of things - reliability generated: by: process:roozbeh.nl/astro-build at: 2026-09-06T00:00:00Z status: stable sources: - id: crossref resource: https://api.crossref.org/works/10.1109/JIOT.2023.3240007 title: Crossref metadata record - id: publisher resource: https://doi.org/10.1109/JIOT.2023.3240007 title: Publisher record (IEEE) - id: pdf resource: https://roozbeh.nl/papers/ReLIEF.pdf title: Author manuscript (PDF) doi: 10.1109/JIOT.2023.3240007 authors: - name: Roozbeh Siyadatzadeh orcid: 0000-0002-2258-4110 - name: Fatemeh Mehrafrooz orcid: 0000-0001-5844-3793 - name: Mohsen Ansari orcid: 0000-0002-4670-8608 - name: Bardia Safaei orcid: 0000-0001-9504-8637 - name: Muhammad Shafique orcid: 0000-0002-2607-8135 - name: Jörg Henkel orcid: 0000-0001-9602-2922 - name: Alireza Ejlali orcid: 0000-0002-5661-3629 year: 2023 published: 2023-06-15 venue: IEEE Internet of Things Journal venue_type: journal publisher: IEEE volume: "10" issue: "12" pages: 10752-10763 web_page: https://roozbeh.nl/publications/relief-rl-task-assignment-fog/ pdf: https://roozbeh.nl/papers/ReLIEF.pdf pdf_version: author bibtex: https://roozbeh.nl/publications/relief-rl-task-assignment-fog.bib citation_count: 52 citation_count_source: Semantic Scholar Graph API, 2026-09-02 --- # ReLIEF: A Reinforcement-Learning-Based Real-Time Task Assignment Strategy in Emerging Fault-Tolerant Fog Computing Roozbeh Siyadatzadeh, Fatemeh Mehrafrooz, Mohsen Ansari, Bardia Safaei, Muhammad Shafique, Jörg Henkel, Alireza Ejlali. IEEE Internet of Things Journal, 2023, pp. 10752-10763. DOI: [10.1109/JIOT.2023.3240007](https://doi.org/10.1109/JIOT.2023.3240007). # Abstract Due to the real-time requirements in several IoT applications, fog computing has emerged to overcome the long latency and other constraints of cloud computing. Due to the high probability of packet loss, energy limitation of IoT devices, and the external disturbances that may frequently occur on the fog infrastructure, the timing constraints of real-time tasks may be compromised. Therefore, the reliability of executing real-time tasks has always been a significant challenge in fog computing. In addition to the correct execution of the tasks, it is also important to execute them before their deadlines according to their real-time classification. State-of-the-art methods generally focus on the delay or functionality of tasks in fog computing systems. However, those methods do not widely focus on the reliability of tasks with real-time constraints in dynamic environments. In this paper, a novel primary backup task assignment strategy based on machine learning (ReLIEF) is proposed to improve the reliability of fog-based IoT systems. To identify suitable nodes for the execution of the primary and backup tasks, ReLIEF employs a Reinforcement Learning (RL) approach, which has an outstanding performance in dynamic environments by establishing a balance between communication delay and workload on each fog device. Based on the simulations, our newly proposed technique has been able to reduce the amount of task dropping rate by up to 84% against the state-of-the-art. Moreover, it is capable of balancing the workload distribution while increasing the reliability of the system by nearly 72% compared with its counterparts. # Key result Reduced task dropping by up to 84% and improved system reliability by nearly 72% in simulation against state-of-the-art strategies. # Cite R. Siyadatzadeh et al., "ReLIEF: A Reinforcement-Learning-Based Real-Time Task Assignment Strategy in Emerging Fault-Tolerant Fog Computing," IEEE Internet of Things Journal, vol. 10, no. 12, pp. 10752-10763, 2023, doi: 10.1109/JIOT.2023.3240007. ```bibtex @article{siyadatzadeh2023relief, author = {Siyadatzadeh, Roozbeh and Mehrafrooz, Fatemeh and Ansari, Mohsen and Safaei, Bardia and Shafique, Muhammad and Henkel, Jörg and Ejlali, Alireza}, title = {{ReLIEF}: A Reinforcement-Learning-Based Real-Time Task Assignment Strategy in Emerging Fault-Tolerant Fog Computing}, journal = {IEEE Internet of Things Journal}, volume = {10}, number = {12}, year = {2023}, pages = {10752--10763}, publisher = {IEEE}, doi = {10.1109/JIOT.2023.3240007}, url = {https://doi.org/10.1109/JIOT.2023.3240007}, } ``` # Files * [Web page](https://roozbeh.nl/publications/relief-rl-task-assignment-fog/) * [Author manuscript (PDF)](https://roozbeh.nl/papers/ReLIEF.pdf) * [AI-generated audio overview (NotebookLM), 5 min](https://roozbeh.nl/audio/ReLIEF.m4a) * [AI-generated video overview (NotebookLM), 7 min](https://roozbeh.nl/videos/ReLIEF.mp4) # Related * [Reinforcement Learning for Reliable Real-Time Fog Systems](../notes/rl-realtime.md) * [My Journey from Bushehr to Leiden](../notes/academic-journey.md) Author record: [Roozbeh Siyadatzadeh](../person/roozbeh-siyadatzadeh.md). --- --- type: Scholarly Article title: "ATLAS: Aging-Aware Task Replication for Multicore Safety-Critical Systems" description: Aging-aware task replication that keeps periodic hard real-time tasks at their reliability target over a multicore system’s lifetime while limiting the temperature that accelerates aging. resource: https://doi.org/10.1109/RTAS58335.2023.00025 tags: - real-time systems - safety-critical systems - task replication - processor aging - thermal management - aging - reliability - multicore generated: by: process:roozbeh.nl/astro-build at: 2026-09-06T00:00:00Z status: stable sources: - id: crossref resource: https://api.crossref.org/works/10.1109/RTAS58335.2023.00025 title: Crossref metadata record - id: publisher resource: https://doi.org/10.1109/RTAS58335.2023.00025 title: Publisher record (IEEE) doi: 10.1109/RTAS58335.2023.00025 authors: - name: Mohsen Ansari orcid: 0000-0002-4670-8608 - name: Sepideh Safari - name: Amir Yeganeh-Khaksar - name: Roozbeh Siyadatzadeh orcid: 0000-0002-2258-4110 - name: Pourya Gohari-Nazari - name: Heba Khdr - name: Muhammad Shafique orcid: 0000-0002-2607-8135 - name: Jörg Henkel orcid: 0000-0001-9602-2922 - name: Alireza Ejlali orcid: 0000-0002-5661-3629 year: 2023 published: 2023-05-09 venue: 2023 IEEE 29th Real-Time and Embedded Technology and Applications Symposium (RTAS) venue_type: conference publisher: IEEE pages: 223-234 web_page: https://roozbeh.nl/publications/atlas-aging-aware-task-replication/ bibtex: https://roozbeh.nl/publications/atlas-aging-aware-task-replication.bib citation_count: 7 citation_count_source: Semantic Scholar Graph API, 2026-09-02 --- # ATLAS: Aging-Aware Task Replication for Multicore Safety-Critical Systems Mohsen Ansari, Sepideh Safari, Amir Yeganeh-Khaksar, Roozbeh Siyadatzadeh, Pourya Gohari-Nazari, Heba Khdr, Muhammad Shafique, Jörg Henkel, Alireza Ejlali. 2023 IEEE 29th Real-Time and Embedded Technology and Applications Symposium (RTAS), 2023, pp. 223-234. DOI: [10.1109/RTAS58335.2023.00025](https://doi.org/10.1109/RTAS58335.2023.00025). # Abstract A major requirement of safety-critical systems is high reliability at low power consumption. Dynamic voltage and frequency (v/f) scaling (DVFS) techniques are widely exploited to reduce power consumption. However, DVFS through downscaling v/f levels has a negative impact on the reliability of the tasks running on the cores, and through upscaling v/f levels has circuit-level aging effects. To achieve high reliability in multicore safety-critical systems, task replication as a fault-tolerant technique is an established way to deal with the negative effect of downscaling v/f levels, but it may accelerate aging effects due to elevating the on-chip temperatures. In this paper, we propose an aging-aware task replication (called ATLAS) method that solves the problem of satisfying the desired reliability target for a set of periodic hard real-time tasks which are executed on a multicore system. The proposed method satisfies the reliability target of the tasks through updating the required number of replicas for each task at different years. We replicate the tasks through our proposed formulas such that the reliability target is satisfied. However, task replication increases the temperature of the system and accelerates aging. To decelerate aging, we attempt to reduce the temperature while mapping and scheduling the tasks. We have also developed a modified demand bound function (DBF) for our aging-aware task replication method to verify scheduling the real-time tasks. Compared to the existing state-of-the-art techniques, experimental results for safety-critical applications on different configurations of multicore systems demonstrate the efficiency and effectiveness of our proposed method. Experiments show that our proposed method improves schedulability on average by 16.1% and reduces the temperature on average by 7.4°C compared to state-of-the-art methods while meeting the system reliability target. # Key result Improved schedulability by 16.1% and reduced temperature by 7.4°C on average against state-of-the-art methods, while meeting the reliability target. # Cite M. Ansari et al., "ATLAS: Aging-Aware Task Replication for Multicore Safety-Critical Systems," in 2023 IEEE 29th Real-Time and Embedded Technology and Applications Symposium (RTAS), San Antonio, TX, USA, 2023, pp. 223-234, doi: 10.1109/RTAS58335.2023.00025. ```bibtex @inproceedings{ansari2023atlas, author = {Ansari, Mohsen and Safari, Sepideh and Yeganeh-Khaksar, Amir and Siyadatzadeh, Roozbeh and Gohari-Nazari, Pourya and Khdr, Heba and Shafique, Muhammad and Henkel, Jörg and Ejlali, Alireza}, title = {{ATLAS}: Aging-Aware Task Replication for Multicore Safety-Critical Systems}, booktitle = {2023 IEEE 29th Real-Time and Embedded Technology and Applications Symposium (RTAS)}, year = {2023}, pages = {223--234}, publisher = {IEEE}, address = {San Antonio, TX, USA}, doi = {10.1109/RTAS58335.2023.00025}, url = {https://doi.org/10.1109/RTAS58335.2023.00025}, } ``` # Files * [Web page](https://roozbeh.nl/publications/atlas-aging-aware-task-replication/) * [AI-generated audio overview (NotebookLM), 16 min](https://roozbeh.nl/audio/ATLAS.m4a) Author record: [Roozbeh Siyadatzadeh](../person/roozbeh-siyadatzadeh.md). --- --- type: Scholarly Article title: Passive Primary/Backup-Based Scheduling for Simultaneous Power and Reliability Management on Heterogeneous Embedded Systems description: Passive primary/backup scheduling on heterogeneous multicores that mixes task mapping across core types and runs backups after primaries to remove execution overlap. resource: https://doi.org/10.1109/TSUSC.2022.3186656 tags: - heterogeneous multicore systems - real-time scheduling - fault tolerance - energy efficiency - reliability - embedded systems - power/energy consumption - thermal design power generated: by: process:roozbeh.nl/astro-build at: 2026-09-06T00:00:00Z status: stable sources: - id: crossref resource: https://api.crossref.org/works/10.1109/TSUSC.2022.3186656 title: Crossref metadata record - id: publisher resource: https://doi.org/10.1109/TSUSC.2022.3186656 title: Publisher record (IEEE) - id: pdf resource: https://roozbeh.nl/papers/tsusc.pdf title: Author manuscript (PDF) doi: 10.1109/TSUSC.2022.3186656 authors: - name: Sina Yari-Karin orcid: 0000-0003-0038-8642 - name: Roozbeh Siyadatzadeh orcid: 0000-0002-2258-4110 - name: Mohsen Ansari orcid: 0000-0002-4670-8608 - name: Alireza Ejlali orcid: 0000-0002-5661-3629 year: 2023 published: 2023-01-01 venue: IEEE Transactions on Sustainable Computing venue_type: journal publisher: IEEE volume: "8" issue: "1" pages: 82-93 web_page: https://roozbeh.nl/publications/passive-primary-backup-scheduling-heterogeneous/ pdf: https://roozbeh.nl/papers/tsusc.pdf pdf_version: author bibtex: https://roozbeh.nl/publications/passive-primary-backup-scheduling-heterogeneous.bib citation_count: 15 citation_count_source: Semantic Scholar Graph API, 2026-09-02 --- # Passive Primary/Backup-Based Scheduling for Simultaneous Power and Reliability Management on Heterogeneous Embedded Systems Sina Yari-Karin, Roozbeh Siyadatzadeh, Mohsen Ansari, Alireza Ejlali. IEEE Transactions on Sustainable Computing, 2023, pp. 82-93. DOI: [10.1109/TSUSC.2022.3186656](https://doi.org/10.1109/TSUSC.2022.3186656). # Abstract In addition to meeting the real-time constraint, power/energy efficiency and high reliability are two vital objectives for real-time embedded systems. Recently, heterogeneous multicore systems have been considered an appropriate solution for achieving joint power/energy efficiency and high reliability. However, power/energy and reliability are two conflict requirements due to the inherent redundancy of fault-tolerance techniques. Also, because of the heterogeneity of the system, the execution of the tasks, especially real-time tasks, in the heterogeneous system is more complicated than the homogeneous system. The proposed method in this paper employs a passive primary/backup technique to preserve the reliability requirement of the system at a satisfactory level and reduces power/energy consumption in heterogeneous multicore systems by considering real-time and peak power constraints. The proposed method attempts to map the primary and backup tasks in a mixed manner to benefit from the execution of the tasks in different core types and schedules the backup tasks after finishing the primary tasks to remove the overlap between the execution of the primary and backup tasks. Compared to the existing state-of-the-art methods, experimental results demonstrate our proposed method’s power efficiency and effectiveness in terms of schedulability. # Key result Lower power consumption and better schedulability than existing methods while meeting real-time, reliability, and peak-power constraints. # Cite S. Yari-Karin, R. Siyadatzadeh, M. Ansari and A. Ejlali, "Passive Primary/Backup-Based Scheduling for Simultaneous Power and Reliability Management on Heterogeneous Embedded Systems," IEEE Transactions on Sustainable Computing, vol. 8, no. 1, pp. 82-93, 2023, doi: 10.1109/TSUSC.2022.3186656. ```bibtex @article{yarikarin2023passive, author = {Yari-Karin, Sina and Siyadatzadeh, Roozbeh and Ansari, Mohsen and Ejlali, Alireza}, title = {Passive Primary/Backup-Based Scheduling for Simultaneous Power and Reliability Management on Heterogeneous Embedded Systems}, journal = {IEEE Transactions on Sustainable Computing}, volume = {8}, number = {1}, year = {2023}, pages = {82--93}, publisher = {IEEE}, doi = {10.1109/TSUSC.2022.3186656}, url = {https://doi.org/10.1109/TSUSC.2022.3186656}, } ``` # Files * [Web page](https://roozbeh.nl/publications/passive-primary-backup-scheduling-heterogeneous/) * [Author manuscript (PDF)](https://roozbeh.nl/papers/tsusc.pdf) * [AI-generated audio overview (NotebookLM), 5 min](https://roozbeh.nl/audio/tsusc.m4a) Author record: [Roozbeh Siyadatzadeh](../person/roozbeh-siyadatzadeh.md). --- --- type: Research Project title: "NeuroSoC: security assessment of an in-memory computing SoC" description: Side-channel security assessment of a PCM-based analog in-memory computing system-on-chip developed by a Horizon Europe consortium of industry and academic partners. resource: https://doi.org/10.3030/101070634 tags: - power side-channel analysis - analog in-memory computing - pcm - risc-v soc - transformers - python - pytorch generated: by: process:roozbeh.nl/astro-build at: 2026-09-06T00:00:00Z status: stable sources: - id: website resource: https://neurosoc.eu/ title: NeuroSoC project website - id: cordis resource: https://doi.org/10.3030/101070634 title: CORDIS grant record - id: cv resource: https://roozbeh.nl/cv.pdf title: Curriculum vitae (PDF) period: Nov 2022 – Feb 2026 role: PhD candidate, hardware security work organization: Leiden University, within the Horizon Europe NeuroSoC consortium programme: Horizon Europe grant_agreement: "101070634" website: https://neurosoc.eu/ partners: - IBM - STMicroelectronics - Bosch - Thales - Ubotica - Benkei - Software Competence Center Hagenberg (SCCH) - ETH Zurich - Leiden University - University of Bologna - University of Patras - University of Pavia - King's College London - Northeastern University London web_page: https://roozbeh.nl/projects/neurosoc/ --- # NeuroSoC: security assessment of an in-memory computing SoC NeuroSoC combined a phase-change-memory analog in-memory computing unit with RISC-V cores in a 28 nm FD-SOI system-on-chip. Fourteen partners took part, including IBM, STMicroelectronics, Bosch, Thales, and ETH Zurich. At Leiden I worked on the security assessment, in a work package shared with IBM and the STMicroelectronics teams in France and Italy: measuring what the analog tiles and their ADCs leak through power, recovering model weights from that leakage, and turning the findings into guidance for protecting models on the chip. # Project NeuroSoC set out to build a flexible computing system in which an analog in-memory-computing neural processing unit is integrated into a multi-processor, functionally safe and secure system-on-chip. The prototype combines a phase-change-memory (PCM) based analog in-memory computing unit with RISC-V processors in 28 nm FD-SOI technology, targeting more than a hundred-fold gains in energy efficiency and compute density for edge-AI workloads. # Role Leiden University was responsible for the security assessment of the system-on-chip. That work sat in the same work package as IBM and STMicroelectronics, with ST teams in France and Italy, and the closest day-to-day collaboration on the security task was with STMicroelectronics France. My PhD work covers the physical side of the assessment: what the analog compute tiles and their data converters leak through power consumption, how far model weights can be reconstructed from that leakage, and what this means for protecting machine-learning models on the chip. # Contributions * **ADC power side-channel analysis of analog in-memory computing tiles.** Built the measurement and analysis pipeline for oscillator-based ADCs, the interface between analog compute tiles and the digital system, and showed that their power traces carry the digital output values. * **Weight extraction with Transformers (TraceFormer).** Combined a Transformer that maps ADC power traces to output values with an input-controlled weight-isolation technique that exposes one stored weight at a time. Published at Euromicro DSD 2025. * **Power traces as transferable knowledge (P2W).** Showed that power traces captured from an embedded SoC can be translated into an approximate weight matrix that gives a new model a head start when training data is scarce. Published at ACM SAC 2026. * **Security of distributed CNN inference at the edge.** Co-authored an evaluation of how CNN partitioning strategies expose input data to an eavesdropper on the link between edge devices. Published at SPACE 2025. # Partners * IBM (industry) * STMicroelectronics (industry) * Bosch (industry) * Thales (industry) * Ubotica (industry) * Benkei (industry) * Software Competence Center Hagenberg (SCCH) (industry) * ETH Zurich (academia) * Leiden University (academia) * University of Bologna (academia) * University of Patras (academia) * University of Pavia (academia) * King's College London (academia) * Northeastern University London (academia) # Publications * [TraceFormer: A Transformer-Based Method for Weight Extraction from AIMC Tiles](../publications/traceformer-weight-extraction-aimc.md) * [P2W: From Power Traces to Weights Matrix - An Unconventional Transfer Learning Approach](../publications/p2w-power-traces-to-weights.md) * [A Security Analysis of CNN Partitioning Strategies for Distributed Inference at the Edge](../publications/security-analysis-cnn-partitioning-edge.md) # Links * [neurosoc.eu](https://neurosoc.eu/) * [Grant record (CORDIS)](https://doi.org/10.3030/101070634) * [Project video](https://www.youtube.com/watch?v=UkPTrqwCrAk) Owner record: [Roozbeh Siyadatzadeh](../person/roozbeh-siyadatzadeh.md). --- --- type: Project title: Thermal management and task scheduling for multicore systems description: How task placement and scheduling shape the thermal behaviour of a multicore system, evaluated with a gem5, McPAT, and HotSpot workflow. resource: https://roozbeh.nl/projects/#project-thermal-aware-task-scheduling tags: - python - gem5 - mcpat - hotspot generated: by: process:roozbeh.nl/astro-build at: 2026-09-06T00:00:00Z status: stable sources: - id: cv resource: https://roozbeh.nl/cv.pdf title: Curriculum vitae (PDF) period: Jun 2021 – Jun 2021 role: Simulation and scheduling study organization: Sharif University of Technology web_page: https://roozbeh.nl/projects/#project-thermal-aware-task-scheduling --- # Thermal management and task scheduling for multicore systems Connected gem5 performance simulation, McPAT power modelling, and HotSpot thermal simulation into one workflow to study how scheduling decisions move heat around a multicore chip and what that costs in performance and power. Owner record: [Roozbeh Siyadatzadeh](../person/roozbeh-siyadatzadeh.md). --- --- type: Project title: Complex-number ALU on FPGA description: A VHDL arithmetic logic unit for complex-number operations, synthesised and verified with Xilinx ISE. resource: https://roozbeh.nl/projects/#project-complex-alu-fpga tags: - vhdl - xilinx ise generated: by: process:roozbeh.nl/astro-build at: 2026-09-06T00:00:00Z status: stable sources: - id: cv resource: https://roozbeh.nl/cv.pdf title: Curriculum vitae (PDF) period: May 2021 – May 2021 role: RTL design and verification web_page: https://roozbeh.nl/projects/#project-complex-alu-fpga --- # Complex-number ALU on FPGA Designed and verified a VHDL arithmetic logic unit for complex-number operations through a full FPGA development flow. Owner record: [Roozbeh Siyadatzadeh](../person/roozbeh-siyadatzadeh.md). --- --- type: Project title: Neural-network inference on FPGA description: An RTL implementation of neural-network inference for resource-constrained edge hardware. resource: https://roozbeh.nl/projects/#project-deep-learning-on-fpga tags: - verilog - vivado - python generated: by: process:roozbeh.nl/astro-build at: 2026-09-06T00:00:00Z status: stable sources: - id: cv resource: https://roozbeh.nl/cv.pdf title: Curriculum vitae (PDF) period: Jan 2021 – Jan 2021 role: RTL implementation web_page: https://roozbeh.nl/projects/#project-deep-learning-on-fpga --- # Neural-network inference on FPGA Explored an RTL implementation of neural-network inference in Verilog for resource-constrained edge hardware, with Python tooling for model preparation. Owner record: [Roozbeh Siyadatzadeh](../person/roozbeh-siyadatzadeh.md). --- --- type: Project title: Reinforcement-learning DVFS manager for multicore platforms description: A reinforcement-learning controller for dynamic voltage and frequency scaling, evaluated on a simulated multicore with Sniper, McPAT, and HotSpot. resource: https://roozbeh.nl/projects/#project-rl-dvfs-manager tags: - python - reinforcement learning - sniper - mcpat - hotspot generated: by: process:roozbeh.nl/astro-build at: 2026-09-06T00:00:00Z status: stable sources: - id: cv resource: https://roozbeh.nl/cv.pdf title: Curriculum vitae (PDF) period: Dec 2020 – Dec 2020 role: Controller design and simulation organization: Sharif University of Technology web_page: https://roozbeh.nl/projects/#project-rl-dvfs-manager --- # Reinforcement-learning DVFS manager for multicore platforms Designed a learning-based controller that picks voltage and frequency levels per core to trade performance, power, and temperature, and evaluated it on a simulated multicore platform built from Sniper, McPAT, and HotSpot. Owner record: [Roozbeh Siyadatzadeh](../person/roozbeh-siyadatzadeh.md). --- --- type: Project title: Distributed VSOP87 planetary positions with MPI description: The VSOP87 planetary-position calculation parallelised across MPI workers in C. resource: https://roozbeh.nl/projects/#project-distributed-vsop87 tags: - c - mpi generated: by: process:roozbeh.nl/astro-build at: 2026-09-06T00:00:00Z status: stable sources: - id: cv resource: https://roozbeh.nl/cv.pdf title: Curriculum vitae (PDF) period: Nov 2020 – Nov 2020 role: Parallel programming web_page: https://roozbeh.nl/projects/#project-distributed-vsop87 --- # Distributed VSOP87 planetary positions with MPI Parallelised the VSOP87 planetary-position calculation across MPI workers to explore distributed numerical computing in C. Owner record: [Roozbeh Siyadatzadeh](../person/roozbeh-siyadatzadeh.md). --- --- type: Project title: FPGA CNN for ECG classification description: A convolutional-neural-network pipeline for ECG classification, from a TensorFlow model to an RTL implementation. resource: https://roozbeh.nl/projects/#project-fpga-cnn-ecg-classification tags: - verilog - python - tensorflow generated: by: process:roozbeh.nl/astro-build at: 2026-09-06T00:00:00Z status: stable sources: - id: cv resource: https://roozbeh.nl/cv.pdf title: Curriculum vitae (PDF) period: Apr 2020 – Apr 2020 role: Model and RTL implementation web_page: https://roozbeh.nl/projects/#project-fpga-cnn-ecg-classification --- # FPGA CNN for ECG classification Implemented a convolutional-neural-network inference pipeline for ECG classification, combining TensorFlow model work with an RTL hardware implementation in Verilog. Owner record: [Roozbeh Siyadatzadeh](../person/roozbeh-siyadatzadeh.md). --- --- type: Project title: Distributed Keras inference over gRPC description: A prototype prediction service that coordinates Keras model inference across networked Python processes with gRPC. resource: https://roozbeh.nl/projects/#project-distributed-keras-inference tags: - python - keras - grpc - distributed systems generated: by: process:roozbeh.nl/astro-build at: 2026-09-06T00:00:00Z status: stable sources: - id: cv resource: https://roozbeh.nl/cv.pdf title: Curriculum vitae (PDF) period: Feb 2020 – Feb 2020 role: Distributed inference prototype web_page: https://roozbeh.nl/projects/#project-distributed-keras-inference --- # Distributed Keras inference over gRPC Split Keras model inference across several Python processes and used gRPC to coordinate prediction requests between them, as a study of distributed inference plumbing. Owner record: [Roozbeh Siyadatzadeh](../person/roozbeh-siyadatzadeh.md). --- --- type: Project title: Facial attribute editing with a GAN description: Controlled facial-attribute editing with a generative adversarial network in TensorFlow. resource: https://roozbeh.nl/projects/#project-facial-attribute-editing-gan tags: - python - tensorflow - gan generated: by: process:roozbeh.nl/astro-build at: 2026-09-06T00:00:00Z status: stable sources: - id: cv resource: https://roozbeh.nl/cv.pdf title: Curriculum vitae (PDF) period: Oct 2019 – Oct 2019 role: Model implementation web_page: https://roozbeh.nl/projects/#project-facial-attribute-editing-gan --- # Facial attribute editing with a GAN Explored controlled facial-attribute editing with a generative adversarial network implemented in TensorFlow. Owner record: [Roozbeh Siyadatzadeh](../person/roozbeh-siyadatzadeh.md). --- --- type: Project title: Sentiment analysis of social-media comments description: Machine-learning sentiment classification of social-media comments in TensorFlow. resource: https://roozbeh.nl/projects/#project-social-media-sentiment-analysis tags: - python - tensorflow generated: by: process:roozbeh.nl/astro-build at: 2026-09-06T00:00:00Z status: stable sources: - id: cv resource: https://roozbeh.nl/cv.pdf title: Curriculum vitae (PDF) period: Aug 2019 – Aug 2019 role: Model implementation web_page: https://roozbeh.nl/projects/#project-social-media-sentiment-analysis --- # Sentiment analysis of social-media comments Built and evaluated machine-learning models for sentiment classification of social-media comments using TensorFlow. Owner record: [Roozbeh Siyadatzadeh](../person/roozbeh-siyadatzadeh.md). --- --- type: Article title: Security Challenges in Analog In-Memory Computing description: How ADC power leakage can expose weights stored in analog in-memory-computing accelerators, and what that means for secure edge AI. resource: https://roozbeh.nl/blog/imc-security/ tags: - hardware-security - aimc - side-channel-analysis generated: by: process:roozbeh.nl/astro-build at: 2026-08-06T00:00:00Z status: stable sources: - id: page resource: https://roozbeh.nl/blog/imc-security/ title: Published note author: human:roozbeh - id: traceformer resource: https://doi.org/10.1109/DSD67783.2025.00092 title: "TraceFormer: A Transformer-Based Method for Weight Extraction from AIMC Tiles" - id: p2w resource: https://doi.org/10.1145/3748522.3779939 title: "P2W: From Power Traces to Weights Matrix - An Unconventional Transfer Learning Approach" author: Roozbeh Siyadatzadeh published: 2024-12-15 updated: 2026-08-06 --- # Security Challenges in Analog In-Memory Computing Analog In-Memory Computing (AIMC) reduces data movement by performing matrix-vector operations close to where neural-network weights are stored. This can improve latency and energy efficiency for suitable inference workloads, but it also changes the hardware attack surface. My PhD research asks a practical question: **what can an attacker learn from the physical behavior of an AIMC accelerator, even without direct access to the stored model?** ## Where the leakage comes from An AIMC tile stores weights as conductance values and produces analog computation results. Those results must normally pass through analog-to-digital converters (ADCs) before the rest of a digital system can use them. The ADCs switch transistors in a data-dependent way. Their power consumption can therefore contain information about the digital values they produce. If an attacker can provide chosen inputs and measure the corresponding power traces, the ADC can become a side-channel leakage point. This is important because model weights are valuable intellectual property. Recovering them may enable model cloning or support follow-on analysis of the model and its implementation. ## TraceFormer: isolating and extracting weights In [TraceFormer](https://doi.org/10.1109/DSD67783.2025.00092), we study this leakage through a two-phase method: 1. A Transformer model learns to translate captured ADC power traces into digital output values. 2. An input-controlled isolation technique exposes the contribution of one stored weight at a time, allowing its value to be inferred from the ADC trace. The experiments use oscillator-based ADCs emulated on real hardware and evaluate the method under different operating conditions. The results demonstrate that ADC power leakage can reveal weights stored in an AIMC tile with high accuracy and robustness in the evaluated setup. This is a physical side-channel attack, not a remote software exploit. Its feasibility depends on the attacker's measurement access, ability to control inputs, the target ADC design, noise, and the countermeasures implemented by the system. ## A related path: power traces as transferable knowledge [P2W](https://doi.org/10.1145/3748522.3779939) explores a related but distinct idea. Instead of using a Transformer to recover one AIMC weight at a time, P2W trains an encoder-decoder neural network to translate power traces from an embedded SoC into an approximate weight matrix. That matrix initializes a new model when only a limited training dataset is available. Together, the two studies show why model protection cannot stop at encrypting a file at rest. The full inference path - memory cells, converters, interconnects, and digital processing - needs to be considered. ## Security design implications Potential defenses should be evaluated against a defined threat model and measured on the target hardware. Relevant research directions include: - reducing data-dependent power leakage in ADCs and peripheral circuits; - randomizing operation order or timing where real-time constraints permit it; - masking or encoding sensitive intermediate values; - detecting abnormal measurement or chosen-input behavior; - testing security across voltage, temperature, process variation, and realistic noise. Each countermeasure has costs in area, latency, energy, accuracy, or design complexity. The useful engineering question is therefore not whether AIMC can be made "secure" in the abstract, but which protections reduce a specific risk to an acceptable level without erasing AIMC's efficiency benefits. ## Sources and further reading - [TraceFormer: A Transformer-Based Method for Weight Extraction from AIMC Tiles](https://doi.org/10.1109/DSD67783.2025.00092) - [P2W: From Power Traces to Weights Matrix](https://doi.org/10.1145/3748522.3779939) - [NeuroSoC project](https://neurosoc.eu/) - [A 64-core mixed-signal in-memory compute chip based on phase-change memory](https://doi.org/10.1038/s41928-023-01010-1) # Related publications * [TraceFormer: A Transformer-Based Method for Weight Extraction from AIMC Tiles](../publications/traceformer-weight-extraction-aimc.md) * [P2W: From Power Traces to Weights Matrix - An Unconventional Transfer Learning Approach](../publications/p2w-power-traces-to-weights.md) Author record: [Roozbeh Siyadatzadeh](../person/roozbeh-siyadatzadeh.md). --- --- type: Article title: "From Power Traces to Model Weights: P2W and TraceFormer" description: Two research methods for learning about embedded neural-network weights through physical power side channels. resource: https://roozbeh.nl/blog/weight-extraction/ tags: - hardware-security - embedded-ml - side-channel-analysis generated: by: process:roozbeh.nl/astro-build at: 2026-08-06T00:00:00Z status: stable sources: - id: page resource: https://roozbeh.nl/blog/weight-extraction/ title: Published note author: human:roozbeh - id: traceformer resource: https://doi.org/10.1109/DSD67783.2025.00092 title: "TraceFormer: A Transformer-Based Method for Weight Extraction from AIMC Tiles" - id: p2w resource: https://doi.org/10.1145/3748522.3779939 title: "P2W: From Power Traces to Weights Matrix - An Unconventional Transfer Learning Approach" author: Roozbeh Siyadatzadeh published: 2024-11-28 updated: 2026-08-06 --- # From Power Traces to Model Weights: P2W and TraceFormer Deploying a neural network on an edge device protects it from ordinary file access, but it does not make the model physically opaque. Inference causes data-dependent electrical activity, and carefully measured power traces can reveal information about the computation. Our work explores two different ways to use that leakage. They address related security questions, but they should not be treated as the same method. ## P2W: unconventional transfer learning [P2W](https://doi.org/10.1145/3748522.3779939) considers a scenario where an existing model runs inside an embedded system-on-chip, direct access to that model is unavailable, and only a limited dataset is available for training a new model. The method follows this pipeline: 1. Capture power traces while the target SoC executes its model on controlled inputs. 2. Train an encoder-decoder neural network to translate those traces into an approximate weight matrix. 3. Use the recovered matrix to initialize a new model. 4. Fine-tune the new model with the limited dataset that is available. In the evaluated experiments, the average accuracy obtained by training only on the limited dataset was 37%. Initializing with P2W and then fine-tuning on the same data raised the average to 97%; across the reported cases, the approach improved accuracy by up to three times over the corresponding classical training setup. P2W is therefore best understood as a proof of concept for **transferring useful model knowledge through a physical side channel**, not as exact bit-for-bit recovery of every parameter. ## TraceFormer: extracting individual AIMC weights [TraceFormer](https://doi.org/10.1109/DSD67783.2025.00092) targets analog in-memory-computing (AIMC) tiles. It focuses on power leakage from the ADCs that convert analog tile outputs into digital values. TraceFormer combines: - a Transformer trained to map ADC power traces to digital output values; and - an input-controlled technique that isolates the effect of one stored weight at a time. That combination allows the value of an isolated weight to be inferred from the corresponding ADC power trace. The paper evaluates oscillator-based ADCs emulated on real hardware and reports high accuracy and robustness under the tested operating conditions. ## What the results do - and do not - establish These studies show that power leakage can expose valuable information about an embedded model. They do not imply that every accelerator can be attacked with the same equipment, trace count, or accuracy. Practical feasibility depends on factors such as: - physical access and measurement bandwidth; - control over model inputs; - the target architecture and converter design; - voltage, temperature, clocking, and environmental noise; - any masking, randomization, filtering, or detection mechanisms. Stating those assumptions matters. A defensible hardware-security result describes the attacker, the measurements, the target, and the limits of the evaluation - not only the headline accuracy. ## Design takeaway Model protection must cover the complete execution path. Encrypting model storage is useful, but weights and intermediate values can still influence observable power while they are being processed. Security reviews for edge-AI accelerators should therefore include physical leakage from memories, data converters, interconnects, and digital compute units. ## Sources - [P2W: From Power Traces to Weights Matrix - An Unconventional Transfer Learning Approach](https://doi.org/10.1145/3748522.3779939) - [P2W preprint](https://arxiv.org/abs/2502.14968) - [TraceFormer: A Transformer-Based Method for Weight Extraction from AIMC Tiles](https://doi.org/10.1109/DSD67783.2025.00092) # Related publications * [TraceFormer: A Transformer-Based Method for Weight Extraction from AIMC Tiles](../publications/traceformer-weight-extraction-aimc.md) * [P2W: From Power Traces to Weights Matrix - An Unconventional Transfer Learning Approach](../publications/p2w-power-traces-to-weights.md) Author record: [Roozbeh Siyadatzadeh](../person/roozbeh-siyadatzadeh.md). --- --- type: Article title: Reinforcement Learning for Reliable Real-Time Fog Systems description: How ReLIEF assigns primary and backup tasks while balancing deadlines, failures, communication delay, and fog-node workload. resource: https://roozbeh.nl/blog/rl-realtime/ tags: - reinforcement-learning - real-time-systems - fog-computing generated: by: process:roozbeh.nl/astro-build at: 2026-08-06T00:00:00Z status: stable sources: - id: page resource: https://roozbeh.nl/blog/rl-realtime/ title: Published note author: human:roozbeh - id: relief resource: https://doi.org/10.1109/JIOT.2023.3240007 title: "ReLIEF: A Reinforcement-Learning-Based Real-Time Task Assignment Strategy in Emerging Fault-Tolerant Fog Computing" author: Roozbeh Siyadatzadeh published: 2024-10-12 updated: 2026-08-06 --- # Reinforcement Learning for Reliable Real-Time Fog Systems Fog computing moves processing closer to IoT devices, reducing the latency of sending every request to a distant cloud. That helps real-time applications, but it introduces a difficult resource-allocation problem: tasks must finish before their deadlines even when communication links or fog nodes fail. My master's research addressed this problem through [ReLIEF](https://doi.org/10.1109/JIOT.2023.3240007), a reinforcement-learning-based primary/backup task-assignment strategy. ## The scheduling problem A useful assignment policy must consider several constraints at once: - a task's execution time and deadline; - the communication delay between devices and fog nodes; - current workload and queueing at each node; - the probability of node or communication failure; - the overhead of creating and transmitting backup tasks. Always sending both a primary and a backup wastes processing and network capacity. Avoiding backups saves resources but can cause a task to miss its deadline after a failure. Static rules also struggle when the workload or network changes. ## How ReLIEF works ReLIEF learns which fog nodes should execute the primary and backup copies of a real-time task. The policy balances communication delay with workload distribution so that assignments can adapt to changing system conditions. A delayed-backup mechanism reduces unnecessary overhead: the backup is held until the remaining time before the deadline approaches the interval needed for communication and execution. If the primary completes successfully, redundant work can be avoided; if it does not, the backup still has time to finish. The result is not a general-purpose operating-system scheduler or a DVFS controller. It is a task-assignment strategy evaluated for fault-tolerant, fog-based IoT systems with real-time constraints. ## Reported evaluation The paper evaluates ReLIEF in simulation against the compared state-of-the-art strategies under different workloads, fog-node counts, and failure rates. The abstract reports: - up to an 84% reduction in task dropping; and - nearly a 72% improvement in system reliability. Those figures apply to the evaluated scenarios and baselines; they are not universal guarantees for every fog deployment. The broader result is that learning-based assignment can improve reliability while distributing workload and respecting task deadlines in a dynamic environment. ## Practical lessons Three lessons from this work carry beyond fog computing: 1. **Define the failure model explicitly.** A scheduling policy is only as meaningful as the node, link, and timing failures it is designed to tolerate. 2. **Include redundancy cost in the decision.** Reliability mechanisms consume computation, bandwidth, and energy; delaying or cancelling unnecessary backup work can matter as much as placement. 3. **Bound the online decision cost.** A policy for real-time systems must produce assignments quickly enough that the scheduling logic does not become part of the deadline problem. Reinforcement learning is useful here because the environment is dynamic, not because it replaces real-time analysis. Deadlines, execution estimates, and schedulability constraints remain central to a credible design. ## Sources - [ReLIEF in IEEE Internet of Things Journal](https://doi.org/10.1109/JIOT.2023.3240007) - [Author PDF](https://roozbeh.nl/papers/ReLIEF.pdf) # Related publications * [ReLIEF: A Reinforcement-Learning-Based Real-Time Task Assignment Strategy in Emerging Fault-Tolerant Fog Computing](../publications/relief-rl-task-assignment-fog.md) Author record: [Roozbeh Siyadatzadeh](../person/roozbeh-siyadatzadeh.md). --- --- type: Article title: Phase-Change Memory for Analog In-Memory Computing description: A practical introduction to PCM conductance, neural-network acceleration, engineering trade-offs, and physical security. resource: https://roozbeh.nl/blog/pcm-future/ tags: - phase-change-memory - aimc - hardware-security generated: by: process:roozbeh.nl/astro-build at: 2026-08-06T00:00:00Z status: stable sources: - id: page resource: https://roozbeh.nl/blog/pcm-future/ title: Published note author: human:roozbeh - id: traceformer resource: https://doi.org/10.1109/DSD67783.2025.00092 title: "TraceFormer: A Transformer-Based Method for Weight Extraction from AIMC Tiles" author: Roozbeh Siyadatzadeh published: 2024-09-05 updated: 2026-08-06 --- # Phase-Change Memory for Analog In-Memory Computing Phase-change memory (PCM) is a non-volatile memory technology that stores information through the electrical resistance of a phase-change material. Its ability to hold multiple conductance levels also makes it useful for analog in-memory computing (AIMC), where memory cells participate directly in neural-network calculations. ## How a PCM cell stores information A PCM device switches between material states with different resistance: - the **crystalline state** has relatively low resistance; - the **amorphous state** has relatively high resistance; - intermediate states can represent additional conductance levels. A SET pulse crystallizes material to lower its resistance. A shorter, higher-power RESET pulse melts and rapidly quenches part of the material into an amorphous, higher-resistance state. A read operation applies a much smaller signal and measures the resulting current without intentionally changing the stored state. The mapping between resistance levels and logical values is a design choice, so it is clearer to discuss high and low resistance than to assume that one state always means binary zero or one. ## From memory cell to matrix-vector multiplication Neural-network layers spend much of their time on matrix-vector multiplication. In a PCM crossbar, conductance values can encode model weights. Input values are applied as voltages or pulse durations, and the resulting column currents approximate dot products through the physical behavior of the array. This approach reduces repeated movement of weights between separate memory and compute units. It is also approximate: device variability, limited precision, conductance drift, programming error, and peripheral circuitry all affect the final result. Large AIMC systems therefore need more than a memory array. They also require data converters, digital processing, communication, calibration, and hardware-aware training. A [64-core PCM-based AIMC chip reported in Nature Electronics](https://doi.org/10.1038/s41928-023-01010-1) is a useful example of that end-to-end integration. ## PCM in NeuroSoC The [NeuroSoC project](https://neurosoc.eu/) developed an MPSoC architecture that combines a PCM-based analog in-memory neural-processing unit with local digital processing and RISC-V host subsystems in 28 nm FD-SOI technology. This hybrid architecture is important because AIMC is not a drop-in replacement for every operation. Analog tiles accelerate suitable matrix operations, while digital cores handle control flow, unsupported operations, communication, and system-level functions. ## Engineering constraints PCM-based AIMC designs must account for several non-idealities: 1. **Conductance drift:** resistance can change over time, affecting stored analog values. 2. **Device and programming variability:** nominally identical cells do not behave exactly alike. 3. **Write cost and endurance:** programming requires energy and repeated writes age the device. 4. **Conversion overhead:** digital-to-analog and analog-to-digital interfaces consume area, time, and energy. 5. **Precision and calibration:** analog computation is approximate and may require hardware-aware training or compensation. These are system-design trade-offs, not reasons to dismiss the technology. They determine which workloads benefit and what support the accelerator needs. ## Security implications Non-volatility protects data from power loss, but it does not by itself protect model confidentiality. Stored weights influence analog outputs, converter activity, timing, and power. In [TraceFormer](https://doi.org/10.1109/DSD67783.2025.00092), we show that power traces from oscillator-based ADCs can reveal digital output values and, with controlled inputs, expose individual weights stored in an AIMC tile under the evaluated attack model. That makes converter and peripheral security part of the memory architecture, not an afterthought. ## Sources and further reading - [NeuroSoC project overview](https://neurosoc.eu/) - [A 64-core mixed-signal in-memory compute chip based on phase-change memory](https://doi.org/10.1038/s41928-023-01010-1) - [Accurate deep neural network inference using computational phase-change memory](https://doi.org/10.1038/s41467-020-16108-9) - [TraceFormer: A Transformer-Based Method for Weight Extraction from AIMC Tiles](https://doi.org/10.1109/DSD67783.2025.00092) # Related publications * [TraceFormer: A Transformer-Based Method for Weight Extraction from AIMC Tiles](../publications/traceformer-weight-extraction-aimc.md) Author record: [Roozbeh Siyadatzadeh](../person/roozbeh-siyadatzadeh.md). --- --- type: Article title: My Journey from Bushehr to Leiden description: Reflections on my academic path from Bushehr to the Netherlands. resource: https://roozbeh.nl/blog/academic-journey/ tags: - personal - academia generated: by: process:roozbeh.nl/astro-build at: 2026-09-06T00:00:00Z status: stable sources: - id: page resource: https://roozbeh.nl/blog/academic-journey/ title: Published note author: human:roozbeh - id: relief resource: https://doi.org/10.1109/JIOT.2023.3240007 title: "ReLIEF: A Reinforcement-Learning-Based Real-Time Task Assignment Strategy in Emerging Fault-Tolerant Fog Computing" author: Roozbeh Siyadatzadeh published: 2024-07-18 updated: 2026-09-06 --- # My Journey from Bushehr to Leiden ## Robotics and Competition During elementary school and high school, before starting my bachelor's degree, I was already drawn to the intersection of hardware and software. My early projects included a firefighting robot. We placed first in a provincial competition and also competed nationally. Those robotics competitions taught me lessons no classroom could: - **Debugging under pressure**: Your robot must work when the judges are watching - **Resource constraints**: Limited budget, limited time, unlimited creativity - **Teamwork**: Hardware and software must work together ## The Beginning: Bushehr (2016-2020) I started my academic journey at Persian Gulf University in Bushehr, a coastal city on the Persian Gulf. The computer engineering program there gave me my first taste of: - Digital circuit design - Programming fundamentals - Neural networks (which would become a recurring theme) ## Sharif University: The Turning Point (2020-2022) Getting into Sharif University's computer architecture program was a dream come true. The Embedded Systems Research Laboratory (ESRLab) became my second home. Under Prof. Ejlali's guidance, I dove deep into: ``` Research Areas @ ESRLab: ├── Real-time systems ├── Fault tolerance ├── Energy efficiency └── Reinforcement learning for embedded systems ``` My master's thesis on reinforcement learning for fog computing opened doors I didn't know existed. The resulting paper, [ReLIEF](https://doi.org/10.1109/JIOT.2023.3240007), was published in the IEEE Internet of Things Journal. ## The PhD Decision Choosing to pursue a PhD meant leaving everything familiar. Then the opportunity at Leiden University came up: working on hardware security with Prof. Mentens and Dr. Stefanov. The [NeuroSoC project](https://neurosoc.eu/) combines everything I care about: - Hardware design (SoC architecture) - Machine learning (neural network accelerators) - Security (protecting AI systems) ## Life in the Netherlands Moving to Leiden has been an adventure: **Challenges:** - Learning Dutch (still working on it: B1 level) - Biking in all weather (including sideways rain) **Rewards:** - World-class research environment - International collaboration - Leiden is an amazing, beautiful historic city ## Advice for the Journey If you're considering a similar path: 1. **Build a strong foundation**: Those undergrad courses matter more than you think 2. **Find good mentors**: I've been fortunate with mine at every stage 3. **Say yes to opportunities**: Even the scary ones 4. **Publish, but also build**: Theory and practice reinforce each other 5. **Stay curious**: The best research comes from genuine interest. As Steve Jobs said, “Stay hungry. Stay foolish.” ## What's Next? As of this 2026 update, I am continuing my PhD at Leiden University and focusing on physical security for embedded AI and analog in-memory-computing systems. I am especially interested in roles where computer architecture, embedded machine learning, and hardware security meet. What matters to me is doing technically rigorous work that can move from an idea to a system that can be measured and trusted. --- *Thanks for reading. Feel free to reach out if you're on a similar journey - I'm always happy to chat.* [Email me](mailto:s.r.siyadatzadeh@liacs.leidenuniv.nl) or see my [Leiden University profile](https://www.universiteitleiden.nl/en/staffmembers/roozbeh-siyadatzadeh). # Related publications * [ReLIEF: A Reinforcement-Learning-Based Real-Time Task Assignment Strategy in Emerging Fault-Tolerant Fog Computing](../publications/relief-rl-task-assignment-fog.md) Author record: [Roozbeh Siyadatzadeh](../person/roozbeh-siyadatzadeh.md).