Phase-change memory (PCM) is a non-volatile memory technology that stores information through the electrical resistance of a phase-change material. Its ability to hold multiple conductance levels also makes it useful for analog in-memory computing (AIMC), where memory cells participate directly in neural-network calculations.
How a PCM cell stores information
A PCM device switches between material states with different resistance:
- the crystalline state has relatively low resistance;
- the amorphous state has relatively high resistance;
- intermediate states can represent additional conductance levels.
A SET pulse crystallizes material to lower its resistance. A shorter, higher-power RESET pulse melts and rapidly quenches part of the material into an amorphous, higher-resistance state. A read operation applies a much smaller signal and measures the resulting current without intentionally changing the stored state.
The mapping between resistance levels and logical values is a design choice, so it is clearer to discuss high and low resistance than to assume that one state always means binary zero or one.
From memory cell to matrix-vector multiplication
Neural-network layers spend much of their time on matrix-vector multiplication. In a PCM crossbar, conductance values can encode model weights. Input values are applied as voltages or pulse durations, and the resulting column currents approximate dot products through the physical behavior of the array.
This approach reduces repeated movement of weights between separate memory and compute units. It is also approximate: device variability, limited precision, conductance drift, programming error, and peripheral circuitry all affect the final result.
Large AIMC systems therefore need more than a memory array. They also require data converters, digital processing, communication, calibration, and hardware-aware training. A 64-core PCM-based AIMC chip reported in Nature Electronics is a useful example of that end-to-end integration.
PCM in NeuroSoC
The NeuroSoC project developed an MPSoC architecture that combines a PCM-based analog in-memory neural-processing unit with local digital processing and RISC-V host subsystems in 28 nm FD-SOI technology.
This hybrid architecture is important because AIMC is not a drop-in replacement for every operation. Analog tiles accelerate suitable matrix operations, while digital cores handle control flow, unsupported operations, communication, and system-level functions.
Engineering constraints
PCM-based AIMC designs must account for several non-idealities:
- Conductance drift: resistance can change over time, affecting stored analog values.
- Device and programming variability: nominally identical cells do not behave exactly alike.
- Write cost and endurance: programming requires energy and repeated writes age the device.
- Conversion overhead: digital-to-analog and analog-to-digital interfaces consume area, time, and energy.
- Precision and calibration: analog computation is approximate and may require hardware-aware training or compensation.
These are system-design trade-offs, not reasons to dismiss the technology. They determine which workloads benefit and what support the accelerator needs.
Security implications
Non-volatility protects data from power loss, but it does not by itself protect model confidentiality. Stored weights influence analog outputs, converter activity, timing, and power.
In TraceFormer, we show that power traces from oscillator-based ADCs can reveal digital output values and, with controlled inputs, expose individual weights stored in an AIMC tile under the evaluated attack model. That makes converter and peripheral security part of the memory architecture, not an afterthought.