---
type: Research Project
title: "NeuroSoC: security assessment of an in-memory computing SoC"
description: Side-channel security assessment of a PCM-based analog in-memory computing system-on-chip developed by a Horizon Europe consortium of industry and academic partners.
resource: https://doi.org/10.3030/101070634
tags:
  - power side-channel analysis
  - analog in-memory computing
  - pcm
  - risc-v soc
  - transformers
  - python
  - pytorch
generated:
  by: process:roozbeh.nl/astro-build
  at: 2026-09-06T00:00:00Z
status: stable
sources:
  - id: website
    resource: https://neurosoc.eu/
    title: NeuroSoC project website
  - id: cordis
    resource: https://doi.org/10.3030/101070634
    title: CORDIS grant record
  - id: cv
    resource: https://roozbeh.nl/cv.pdf
    title: Curriculum vitae (PDF)
period: Nov 2022 – Feb 2026
role: PhD candidate, hardware security work
organization: Leiden University, within the Horizon Europe NeuroSoC consortium
programme: Horizon Europe
grant_agreement: "101070634"
website: https://neurosoc.eu/
partners:
  - IBM
  - STMicroelectronics
  - Bosch
  - Thales
  - Ubotica
  - Benkei
  - Software Competence Center Hagenberg (SCCH)
  - ETH Zurich
  - Leiden University
  - University of Bologna
  - University of Patras
  - University of Pavia
  - King's College London
  - Northeastern University London
web_page: https://roozbeh.nl/projects/neurosoc/
---

# NeuroSoC: security assessment of an in-memory computing SoC

NeuroSoC combined a phase-change-memory analog in-memory computing unit with RISC-V cores in a 28 nm FD-SOI system-on-chip. Fourteen partners took part, including IBM, STMicroelectronics, Bosch, Thales, and ETH Zurich. At Leiden I worked on the security assessment, in a work package shared with IBM and the STMicroelectronics teams in France and Italy: measuring what the analog tiles and their ADCs leak through power, recovering model weights from that leakage, and turning the findings into guidance for protecting models on the chip.

# Project

NeuroSoC set out to build a flexible computing system in which an analog in-memory-computing neural processing unit is integrated into a multi-processor, functionally safe and secure system-on-chip. The prototype combines a phase-change-memory (PCM) based analog in-memory computing unit with RISC-V processors in 28 nm FD-SOI technology, targeting more than a hundred-fold gains in energy efficiency and compute density for edge-AI workloads.

# Role

Leiden University was responsible for the security assessment of the system-on-chip. That work sat in the same work package as IBM and STMicroelectronics, with ST teams in France and Italy, and the closest day-to-day collaboration on the security task was with STMicroelectronics France. My PhD work covers the physical side of the assessment: what the analog compute tiles and their data converters leak through power consumption, how far model weights can be reconstructed from that leakage, and what this means for protecting machine-learning models on the chip.

# Contributions

* **ADC power side-channel analysis of analog in-memory computing tiles.** Built the measurement and analysis pipeline for oscillator-based ADCs, the interface between analog compute tiles and the digital system, and showed that their power traces carry the digital output values.
* **Weight extraction with Transformers (TraceFormer).** Combined a Transformer that maps ADC power traces to output values with an input-controlled weight-isolation technique that exposes one stored weight at a time. Published at Euromicro DSD 2025.
* **Power traces as transferable knowledge (P2W).** Showed that power traces captured from an embedded SoC can be translated into an approximate weight matrix that gives a new model a head start when training data is scarce. Published at ACM SAC 2026.
* **Security of distributed CNN inference at the edge.** Co-authored an evaluation of how CNN partitioning strategies expose input data to an eavesdropper on the link between edge devices. Published at SPACE 2025.

# Partners

* IBM (industry)
* STMicroelectronics (industry)
* Bosch (industry)
* Thales (industry)
* Ubotica (industry)
* Benkei (industry)
* Software Competence Center Hagenberg (SCCH) (industry)
* ETH Zurich (academia)
* Leiden University (academia)
* University of Bologna (academia)
* University of Patras (academia)
* University of Pavia (academia)
* King's College London (academia)
* Northeastern University London (academia)

# Publications

* [TraceFormer: A Transformer-Based Method for Weight Extraction from AIMC Tiles](../publications/traceformer-weight-extraction-aimc.md)
* [P2W: From Power Traces to Weights Matrix - An Unconventional Transfer Learning Approach](../publications/p2w-power-traces-to-weights.md)
* [A Security Analysis of CNN Partitioning Strategies for Distributed Inference at the Edge](../publications/security-analysis-cnn-partitioning-edge.md)

# Links

* [neurosoc.eu](https://neurosoc.eu/)
* [Grant record (CORDIS)](https://doi.org/10.3030/101070634)
* [Project video](https://www.youtube.com/watch?v=UkPTrqwCrAk)

Owner record: [Roozbeh Siyadatzadeh](../person/roozbeh-siyadatzadeh.md).